1. Technical Field
The embodiments described herein relate to a test circuit, and more particularly, to a test circuit for supporting a concurrent test mode that can reduce the test time for a semiconductor memory.
2. Related Art
Presently, there are limited test capabilities for testing a semiconductor memory once it has been packaged. In this regard, a semiconductor memory package has an NC (no connection) pin, through which various test signals can be applied for various test modes. The various test modes allow various signals in the semiconductor memory to be monitored to ensure that the semiconductor memory does not contain a defect that will result in improper operation.
FIG. 1 is a block diagram illustrating a conventional test circuit. Referring to FIG. 1, the conventional test circuit includes an address decoder 10, a latch block 20 and a driving block 30.
The address decoder 10 typically decodes test mode input signals “T<0:2>”. In detail, the address decoder 10 receives and decodes the 3-bit signal test mode input signal “T<0:2>”, and then provides six decoding signals based thereon. The latch block 20 then includes six latch units 21 to 26 corresponding to the six decoding signals. The driving block 30 includes six driving units 31 to 36 corresponding to the six latch units 21 to 26.
Hereinafter, an operation of the conventional test circuit of FIG. 1 will be described in detail. When defect analysis is performed, a test mode set signal “TMSET”, which is used to test an operation of a semiconductor memory, is applied to the address decoder 10 through an NC pin. When the test mode set signal is activated, the semiconductor memory is switched from a normal operation mode to a test mode. The address decoder 10 then decodes the received test mode input signals “T<0:2>”. The decoded signals are transmitted to one of the latch units 21 to 26 of the latch block 20 and then used to drive one of the driving units 31 to 36 of the driving block 30. Thus, the semiconductor memory performs a specific test in accordance with various test modes, such as test modes TM1 to TM6.
As described above, the conventional test circuit can implement only one test mode at a time. In other words, although various test modes exist, only one set of signals can be input, i.e., only one test mode can be implemented at any given time. In order to implement the various test modes, the test mode input signals must be continuously applied to the address decoder 10, which increases the overall test time.